1. Field
Exemplary embodiments of the present invention relate to a nonvolatile memory device, and more particularly, to a nonvolatile memory device including a plurality of memory cells stacked perpendicularly from a substrate and a method for fabricating the same.
2. Description of the Related Art
A nonvolatile memory device maintains data stored therein even when power supply is cut off and a variety of nonvolatile memory devices, for example, a NAND-type flash memory and the like are widely used.
Recently, as the improvement in integration degree of a two-dimensional (2D) memory device in which a plurality of memory cells are formed as a single layer over a silicon substrate approaches its limit, a variety of 3D memory volatile memory devices in which a plurality of memory cells are stacked perpendicularly from a silicon substrate have been proposed.
FIGS. 1A and 16 illustrate a conventional nonvolatile memory device. FIG. 1A is a plan view of the conventional nonvolatile memory device, and FIG. 16 is a cross-sectional view taken along line A-A′ of FIG. 1A.
Referring to FIGS. 1A and 16, a plurality of semiconductor pillars 11 are disposed over a substrate 10 to extend in a direction perpendicular to the substrate 10. The plurality of semiconductor pillars 11 are arranged in a matrix shape along first and second directions. Furthermore, a stacked structure in which a plurality of insulation layers 12 and conductive layers 13 are alternately stacked is disposed over the substrate 10. The stacked structure is disposed to surround the semiconductor pillars 11. Between the stacked structure and the semiconductor pillar 11, a memory layer 14 may be interposed. The memory layer 14 serves to store data by storing or discharging electric charges. One semiconductor pillar 11, one conductive layer 13 contacted with the semiconductor pillar 11, and the memory layer 14 interposed therebetween may construct one memory cell MC. As a result, it may be seen that a plurality of memory cells MC are stacked in a perpendicular direction from the substrate 10.
The stacked structure of the insulation layers 12 and the conductive layers 13 be extended in the second direction while surrounding the semiconductor pillars 11 arranged in the second direction. The stacked structures surrounding the semiconductor pillars 11 adjacent in the first direction, respectively, are isolated from each other by a slit S positioned between the two semiconductor pillars 11. This is done to individually operate memory cells MC adjacent in the first direction, even though the semiconductor pillars 11 arranged in the first direction are connected to the same interconnection, for example, the same bit line.
However, when the slit S is positioned between the stacked structures, the stacked structures may lean as the height of the stacked structures is increased to improve the integration degree of the device.
In order to prevent the stacked structures from leaning the process of forming the stacked structures and the slit S may be performed for multiple times. In this case, however, the number of processes and the fabrication cost may be increased.